1. Field of the Invention
The invention relates to semiconductor technology and in particular to fabrication of a semiconductor device with thin gate spacer capable of increasing spacer merge window while maintaining device performance.
2. Description of the Related Art
In current integrated circuit technology, semiconductor device manufacturers are constantly improving device performance while lowering manufacturing cost. Accordingly, semiconductor device sizes have been continuously reduced so that more devices can be formed on a single chip. However, in reducing device size other factors arise to limit performance. For example, since Metal-Oxide-Metal (MOS) transistors are widely used in semiconductor devices, as the semiconductor devices size is reduced, the gate electrode width, gate-to-gate spacing and gate-to contact spacing are decreased, inducing short channel effect (SCE) and causing gate spacer merge.
Such an adverse effect (i.e. SCE) can result in decreased source-drain break-down voltage, increasing junction parasitic capacitance and unstable threshold voltage and is difficult to control due to source/drain dopant lateral diffusion in reduced device size. Additionally, gate spacer merge results in contact hole failure, such that the integrated circuit is opened.
The gate spacer merge window is limited by the deposition thickness of the film for gate spacer formation. To avoid gate spacer merge, thinner spacers are widely used. However, to control the SCE for the semiconductor device with thinner gate spacer, the source/drain implant energy must be reduced to reduce source/drain dopant lateral diffusion, resulting in reduced source/drain junction depth. In such a case, junction leakage induced by silicide formed on source/drain regions may be aggravated. Accordingly, balance must be struck between source/drain junction depth and gate spacer merge window.
Thus, there exists a need for an improved method for fabricating a semiconductor device to increase gate spacer merge window without SCE degradation.